S75WS256NDFBAWMB datasheet(142/216 Pages) SPANSION

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140

S75WS256Nxx Based MCPs

S75WS-N-00_00_A0 February 17, 2005

Data

Sheet

Notes:

1. RDY active with data (D8 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (D8 = 1 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.

4. There will be an additional 4/8 wait state latency for 54/80 Mhz respectively.

Figure 25.17 Latency with Boundary Crossing

Wait State Configuration Register Setup

Note: Figure assumes address D0 is not at an address boundary.

Figure 25.18 Example of Wait States Insertion

CR1.0, CR0.13, CR0.12, CR0.11= 1101 ⇒

13 total

CR1.0, CR0.13, CR0.12, CR0.11= 1100 ⇒

12 total

CR1.0, CR0.13, CR0.12, CR0.11= 1011 ⇒

11 total

CR1.0, CR0.13, CR0.12, CR0.11= 1010 ⇒

10 total

CR1.0, CR0.13, CR0.12, CR0.11= 1001 ⇒

9 total

CR1.0, CR0.13, CR0.12, CR0.11= 1000 ⇒

8 total

CR1.0, CR0.13, CR0.12, CR0.11= 0101 ⇒

7 total

CR1.0, CR0.13, CR0.12, CR0.11= 0100 ⇒

6 total

CR1.0, CR0.13, CR0.12, CR0.11= 0011 ⇒

5 total

CR1.0, CR0.13, CR0.12, CR0.11= 0010 ⇒

4 total

CR1.0, CR0.13, CR0.12, CR0.11= 0001 ⇒

3 total

CLK

Address (hex)

C508

C509

C510

C511

C512

C513

C514

C515

D508

D509

D510

D511

D512

D513

D514

(stays high)

AVD#

RDY(1)

Data

OE#,

CE#

(stays low)

Address boundary occurs every 512 words, beginning at address

0001FFh: (0002FFh, 0003FFh, etc.) Address 000000h is also a boundary crossing.

1FC

1FD

1FE

1FF

200

201

202

203

latency

RDY(2)

latency

tRACC

Data

AVD#

OE#

CLK

total number of clock cycles

following AVD# falling edge

Rising edge of next clock cycle

following last wait state triggers

next burst data

number of clock cycles

programmed

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