S75WS256NDFBAWMB datasheet(162/216 Pages) SPANSION

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S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

Ad van c e

Inf o rmation

31.2

Bus Configuration Register

The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode

operation is enabled by a bit contained in the RCR. Table 31.1 below describes the control bits in

the BCR. At powerup, the BCR is set to 9D4Fh.

The BCR is accessed using CRE and A[19] High.

Table 31.1 Bus Configuration Register Definition

Note: Burst wrap and length apply to Read operations only.

A13

Latency

Counter

Initial

Latency

WAIT

Polarity

Output

Impedance

Burst

Wrap

(BW)

(Note)

A12 A11

A10

A2 A1 A0

Output Impedance

Full Drive (default)

1/2 Drive

1/4 Drive

Reserved

BCR[5]

BCR[4]

Burst

Length

(BL)

(Note)

Reserved Reserved

Operating

Mode

WAIT Polarity

Active LOW

Active HIGH (default)

BCR[10]

Reserved

22–20

A14

A15

A[18:16]

18–16

Select

Reserved

A19

A[22:20]

Reserved

Must be set to "0"

All must be set to "0"

Operating Mode

Synchronous burst access mode

Asynchronous access mode (default)

BCR[15]

Select RCR

Select BCR

BCR[19]

Burst Wrap (Note)

Burst wraps within the burst length

Burst no wrap (default)

BCR[3]

Must be set to "0"

Setting is ignored

WAIT

Configuration

(WC)

BCR[12] BCR[11] Latency Counter

BCR[13]

Code 0–Reserved

Code 1–Reserved

Code 2

Code 3 (Default)

Code 4

Code 5

Code 6

Code 7–Reserved

WAIT Configuration

Asserted during delay

Asserted one data cycle before delay (default)

BCR[8]

BCR[1] BCR[0] Burst Length (Note)

BCR[2]

4 words

8 words

16 words

Continuous burst (default)

Reserved

Must be set to "0"

Others

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