S75WS256NDFBAWMB datasheet(159/216 Pages) SPANSION

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February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

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Information

31 Configuration Registers

Two user-accessible configuration registers define the device operation. The bus configuration

identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR)

is used to control how refresh is performed on the DRAM array. These registers are automatically

loaded with default settings during power-up, and can be updated any time the devices are op-

erating in a standby state.

31.1

Access Using CRE

The configuration registers can be written to using either a synchronous or an asynchronous op-

eration when the configuration register enable (CRE) input is High (see Figure 31.1 and

Figure 31.2). When CRE is Low, a Read or Write operation will access the memory array. The reg-

ister values are written via address pins A[21:0]. In an asynchronous Write, the values are

latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever oc-

curs first; LB# and UB# are Don’t Care. The BCR is accessed when A[19] is High; the RCR is

accessed when A[19] is Low. For Reads, address inputs other than A[19] are Don’t Care, and reg-

ister bits 15:0 are output on DQ[15:0].

S75WS256NDFBAWMB Datasheet(PDF) 159 Page - SPANSION