S75WS256NDFBAWMB datasheet(156/216 Pages) SPANSION

156 / 216 page

154

S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

Ad van c e

Inf o rmation

not be transferred to the RAM array and the internal value will remain unchanged. During an asyn-

chronous Write cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or

UB#, whichever occurs first.

When both the LB# and UB# are disabled (High) during an operation, the device will disable the

data bus from receiving or transmitting data. Although the device will seem to be deselected, it

remains in an active mode as long as CE# remains Low.

Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.

Figure 29.7 Refresh Collision During Read Operation

Additional WAIT states inserted to allow refresh completion.

CLK

A[22:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

LB#/UB#

Don't care

Undefined

Legend:

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

High-Z

VOH

VOL

D[0]

D[1]

D[2]

D[3]

VOH

VOL

Address

Valid

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