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TMP89FS60 Datasheet(PDF) 114 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 114 Page - Toshiba Semiconductor |
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114 / 410 page ![]() Page 100 8. I/O Ports 8.3 I/O Port Registers TMP89FS60 RA005 Figure 8-4 Port P1 Output latch (for each bit) EN P1DR write P10 RIN2 RIN3 RIN3 R Note1 : R = 100 Ω (typ.) Note2 : RIN2 = 220k Ω (typ.) Note3 : RIN3 = 50k Ω (typ.) P1PRD read Input/output control (for each bit) P1CR write Programmable pull-up resistor Reset pull-up resistor VDD VDD VDD Pull-up control (for each bit) P1PU write Output latch (for each bit) P1DR write SYSCR1<STOP> SYSCR3<RSTDIS> SYSCR4 B2H write SYSCR1<OUTEN> Reset signal Reset signal P1i R Note1 : R = 100 Ω (typ.) Note2 : RIN3 = 50k Ω (typ.) Note3 : i = 1 ~ 3 INT0, INT1, INT5, STOP P1PRD read In case of P11 In case of P12 and P13 Input/output control (for each bit) P1CR write Programmable pull-up resistor VDD VDD Pull-up control (for each bit) P1PU write Interrupt STOP control Peripheral functions Low-voltage detection reset 1 signal Low-voltage detection reset 2 signal Watchdog timer reset signal System clock reset signal Trimming data reset signal Flash standby reset signal Power-on reset signal Reset 1 Reset 2 |
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