TMP89FS60 datasheet(189/410 Pages) TOSHIBA

189 / 410 page

Page 175

TMP89FS60

RA002

14.4 Functions

Timer counters TC00 and TC01 have 8-bit modes in which they are used independently and 16-bit modes in which

they are cascaded.

The 8-bit modes include four operation modes; the 8-bit timer mode, the 8-bit event counter mode, the 8-bit pulse

width modulation output (PWM) mode and the 8-bit programmable pulse generated output (PPG) mode.

The 16-bit modes include four operation modes; the 16-bit timer mode, the 16-bit event counter mode, the 12-bit

PWM mode and the 16-bit PPG mode.

14.4.1 8-bit timer mode

In the 8-bit timer mode, the up-counter counts up using the internal clock, and interrupts can be generated

regularly at specified times. The operation of TC00 is described below, and the same applies to the operation of

TC01. (Replace TC00- by TC01-).

14.4.1.1 Setting

TC00 is put into the 8-bit timer mode by setting T00MOD<TCM0> to "00" or "01", T001CR<TCAS>

to "0" and T00MOD<EIN0> to "0". Select the source clock at T00MOD<TCK0>. Set the count value to

be used for the match detection as an 8-bit value at the timer register T00REG.

Set T00MOD<DBE0> to "1" to use the double buffer.

Setting T001CR<T00RUN> to "1" starts the operation. After the timer is started, writing to T00MOD

becomes invalid. Be sure to complete the required mode settings before starting the timer.

14.4.1.2 Operation

Setting T001CR<T00RUN> to "1" allows the 8-bit up counter to increment based on the selected inter-

nal source clock. When a match between the up counter value and the T00REG set value is detected, an

INTT00 interrupt request is generated and the up counter is cleared to "0x00". After being cleared, the up

counter restarts counting. Setting T001CR<T00RUN> to "0" during the timer operation makes the up

counter stop counting and be cleared to "0x00".

14.4.1.3 Double buffer

The double buffer can be used for T00REG by setting T00MOD<DBE0>. The double buffer is disabled

by setting T00MOD<DBE0> to "0" or enabled by setting T00MOD<DBE0> to "1".

• When the double buffer is enabled

When a write instruction is executed on T00REG during the timer operation, the set value is

initially stored in the double buffer, and T00REG is not immediately updated. T00REG com-

pares the previous set value with the up counter value. When the values match, an INTT00

interrupt request is generated and the double buffer set value is stored in T00REG. Subse-

quently, the match detection is executed using a new set value.

When a write instruction is executed on T00REG while the timer is stopped, the set value is

immediately stored in both the double buffer and T00REG.

• When the double buffer is disabled

When a write instruction is executed on T00REG during the timer operation, the set value is

immediately stored in T00REG. Subsequently, the match detection is executed using a new set

value.

TMP89FS60 Datasheet(PDF) 189 Page - Toshiba Semiconductor

TMP89FS60 Datasheet(HTML) 189 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL