TMP89FS60 datasheet(191/410 Pages) TOSHIBA

191 / 410 page

Page 177

TMP89FS60

RA002

Figure 14-2 Timer Mode Timing Chart

Figure 14-3 Operation When T00REG and the Up Counter Have the Same Value

Source clock

Counter

Timer start

Write to T00REG

Match detection

Write m

Write n

Reflected by writing to T00REG

Reflected by

an interrupt

Reflected at the same time

as data is written into T00REG

while the timer is stopped

Counter clear

INTT00 interrupt request

234

m-1

T00REG

T001CR<T00RUN>

Timer stop

Match detection

Counter clear

n-1

T00MOD<DBE0>

When the double buffer is disabled (T00MOD<DBE0>=”0”)

Source clock

Counter

Timer start

Write to T00REG

Match detection

Write m

Write n

Counter clear

INTT00 interrupt request

234

m-1

T00REG

T001CR<T00RUN>

Double buffer

Match detection

Counter clear

m-1

n-1

T00MOD<DBE0>

When the double buffer is enabled (T00MOD<DBE0>=”1”)

Source clock

Counter

n-4

n-5

n-2

Write to T00REG

Write n-2

INTT00 interrupt request

n-3

n-2

T00REG

Match detection

Counter clear

T00MOD<DBE0>

TMP89FS60 Datasheet(PDF) 191 Page - Toshiba Semiconductor

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