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TMP89FS60 Datasheet(PDF) 192 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 192 Page - Toshiba Semiconductor |
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192 / 410 page ![]() Page 178 14. 8-bit Timer Counter (TC0) TMP89FS60 RA002 14.4.2 8-bit event counter mode In the 8-bit event counter mode, the up counter counts up at the falling edge of the input to the TC00 or TC01 pin. The operation of TC00 is described below, and the same applies to the operation of TC01. 14.4.2.1 Setting TC00 is put into the 8-bit event counter mode by setting T00MOD<TCM0> to "00", T001CR<TCAS> to "0" and T00MOD<EIN0> to "1". Set the count value to be used for the match detection as an 8-bit value at the timer register T00REG. Set T00MOD<DBE0> to "1" to use the double buffer. Setting T001CR<T00RUN> to "1" starts the operation. After the timer is started, writing to T00MOD becomes invalid. Be sure to complete the required mode settings before starting the timer. 14.4.2.2 Operation Setting T001CR<T00RUN> to "1" allows the 8-bit up counter to increment at the falling edge of the TC00 pin. When a match between the up-counter value and the T00REG set value is detected, an INTT00 interrupt request is generated and the up counter is cleared to "0x00". After being cleared, the up counter restarts counting. Setting T001CR<T00RUN> to "0" during the timer operation makes the up counter stop counting and be cleared to "0x00". The maximum frequency to be supplied is fcgck/22 [Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/24 [Hz] (in SLOW1/2 or SLEEP1 mode), and a pulse width of two machine cycles or more is required at both the "H" and "L" levels. 14.4.2.3 Double buffer Refer to "14.4.1.3 Double buffer". (Example) Operate TC00 in the 8-bit event counter mode and generate an interrupt each time 16 falling edges are detected at the TC00 pin. LD (POFFCR0),0x10 ; Sets TC001EN to "1" DI ; Sets the interrupt master enable flag to "disable" SET (EIRH).4 ; Sets the INTTC00 interrupt enable register to "1" EI ; Sets the interrupt master enable flag to "enable" LD (T00MOD),0xC4 ; Selects to the 8-bit event counter mode LD (T00REG),0x10 ; Sets the timer register SET (T001CR).0 ; Starts TC00 |
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