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TMP89FS60 Datasheet(PDF) 190 Page - Toshiba Semiconductor

Part # TMP89FS60
Description  8 Bit Microcontroller
PDF  410 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP89FS60 Datasheet(HTML) 190 Page - Toshiba Semiconductor

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Page 176
14. 8-bit Timer Counter (TC0)
TMP89FS60
RA002
If the value set to T00REG is smaller than the up counter value, the match detection is exe-
cuted using a new set value after the up counter overflows. Therefore, the interrupt request
interval may be longer than the selected time. If the value set to T00REG is equal to the up
counter value, the match detection is executed immediately after data is written into T00REG.
Therefore, the interrupt request interval may not be an integral multiple of the source clock
(Figure 14-3). If these are problems, enable the double buffer.
When a write instruction is executed on T00REG while the timer is stopped, the set value is
immediately stored in T00REG.
When a read instruction is executed on T00REG, the last value written into T00REG is read out, regard-
less of the T00MOD<DBE0> setting.
Table 14-5 8-bit Timer Mode Resolution and Maximum Time Setting
T00MOD
<TCK0>
Source clock [Hz]
Resolution
Maximum time setting
NORMAL1/2 or IDLE1/2 mode
SLOW1/2 or
SLEEP1 mode
fcgck=8MHz
fs=32.768KHz
fcgck=8MHz
fs=32.768KHz
SYSCR1<DV9CK>
= "0"
SYSCR1<DV9CK>
= "1"
000
fcgck/211
fs/24
fs/24
256
µs488.2µs
65.3ms
124.5ms
001
fcgck/210
fs/23
fs/23
128
µs244.1µs
32.6ms
62.3ms
010
fcgck/28
fcgck/28
-32
µs
-
8.2ms
-
011
fcgck/26
fcgck/26
-8
µs
-
2.0ms
-
100
fcgck/24
fcgck/24
-2
µs
-
510
µs-
101
fcgck/22
fcgck/22
-
500ns
-
127.5
µs-
110
fcgck/2
fcgck/2
-
250ns
-
63.8
µs-
111
fcgck
fcgck
fs/22
125ns
122.1
µs31.9µs31.1ms
(Example) Operate TC00 in the 8-bit timer mode with the operation clock of fcgck/22 [Hz] and generate interrupts at 64
µs intervals
(fcgck = 8 MHz)
LD
(POFFCR0),0x10
; Sets TC001EN to "1"
DI
; Sets the interrupt master enable flag to "disable"
SET
(EIRH).4
; Sets the INTTC00 interrupt enable register to "1"
EI
; Sets the interrupt master enable flag to "enable"
LD
(T00MOD),0xE8
; Selects the 8-bit timer mode and fcgck/22
LD
(T00REG),0x80
; Sets the timer register (64
µs / (22/fcgck) = 0x80)
SET
(T001CR).0
; Starts TC00



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