TMP89FS60 datasheet(196/410 Pages) TOSHIBA

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Page 182

14. 8-bit Timer Counter (TC0)

TMP89FS60

RA002

Subsequently, the up counter continues counting up. When the up counter value reaches 128, an over-

flow occurs and the up counter is cleared to "0x00". At the same time, the output of the PWM0 pin is

reversed. When T00MOD<TFF0> is "0", the PWM0 pin changes from the "H" to "L" level. When

T00MOD<TFF0> is "1", the PWM0 pin changes from the "L" to "H" level. If the 2

× n-th overflow occurs

at this time, an INTT00 interrupt request is generated. (No interrupt request is generated at the 2

× n-th -1

overflow.) Subsequently, the up counter continues counting up.

When T001CR<T00RUN> is set to "0" during the timer operation, the up counter is stopped and

cleared to "0x00". The PWM0 pin returns to the level selected at T00MOD<TFF0>.

Figure 14-6 8-bit PWM Mode Timing Chart

(Example) Operate TC00 in the 8-bit PWM mode with the operation clock of fcgck/2 and output a duty pulse nearly equivalent to

11.625

µs (fcgck = 8 MHz)

(Actually, output a total duty pulse of 23.25

µs in 2 cycles (128 µs))

SET

(P7FC).0

; Sets P7FC0 to "1"

SET

(P7CR).0

; Sets P7CR0 to "1"

(POFFCR0),0x10

; Sets TC001EN to "1"

; Sets the interrupt master enable flag to "disable"

SET

(EIRH).4

; Sets the INTTC00 interrupt enable register to "1"

; Sets the interrupt master enable flag to "enable"

(T00MOD),0xF2

; Selects the 8-bit PWM mode and fcgck/2

(T00PWM),0x5D

; Sets the timer register (duty pulse)

; (11.625

µs × 2) / (2/fcgck) = 0x5D

SET

(T001CR).0

; Starts TC00

Source clock

Counter

Timer start

(Duty pulse)

128 counts

(Cycle 1)

128 counts

(Cycle 2)

128 counts

(Cycle 3)

128 counts

(Cycle 4)

Write to T00PWM

Double buffer

Write m

Write r

Write s

Becomes the level selected at

TFF0 while the timer is stopped

Reflected by an

interrupt request

Interrupt request

Reflected by an

interrupt request

Returns to the

level selected

at TFF0

INTT00 interrupt

request

m+1

T00PWM

T00PWM

<PWMAD>

T001CR<T00RUN>

No interrupt request

is generated

No interrupt request

is generated

128

Timer stop

Match detection

m+1

128

r+1

128

r+1

128

Match detection

Counter

clear

Overflow

Counter

clear

Counter

clear

Counter

clear

T00MOD<TFF0>

PWM0 pin output

When the double buffer is enabled (T00MOD<DBE0>=”1”)

(Duty pulse)

r+1

(Duty pulse)

Additional pulse

Match detection

TMP89FS60 Datasheet(PDF) 196 Page - Toshiba Semiconductor

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