TMP89FS60 datasheet(200/410 Pages) TOSHIBA

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Page 186

14. 8-bit Timer Counter (TC0)

TMP89FS60

RA002

14.4.4.2 Operation

Setting T001CR<T00RUN> to "1" allows the up counter to increment based on the selected source

clock. When a match between the internal up counter value and the value set to T00PWM is detected, the

output of the PPG0 pin is reversed. When T00MOD<TFF0> is "0", the PPG0 pin changes from the "L" to

"H" level. When T00MOD<TFF0> is "1", the PPG0 pin changes from the "H" to "L" level.

Subsequently, the up counter continues counting up. When a match between the up counter value and

T00REG is detected, the output of the PPG0 pin is reversed again. When T00MOD<TFF0> is "0", the

PPG0

pin changes from the "H" to "L" level. When T00MOD<TFF0> is "1", the PPG0 pin changes from

the "L" to "H" level. At this time, an INTT00 interrupt request is generated.

When T001CR<T00RUN> is set to "0" during the operation, the up counter is stopped and cleared to

"0x00". The PPG0 pin returns to the level selected at T00MOD<TFF0>.

14.4.4.3 Double buffer

The double buffer can be used for T00PWM and T00REG by setting T00MOD<DBE0>. The double

buffer is disabled by setting T00MOD<DBE0> to "0" or enabled by setting T00MOD<DBE0> to "1".

• When the double buffer is enabled

When a write instruction is executed on T00PWM (T00REG) during the timer operation, the

set value is first stored in the double buffer, and T00PWM (T00REG) is not updated immedi-

ately. T00PWM (T00REG) compares the previous set value with the up counter value. When

an INTT00 interrupt request is generated, the double buffer set value is stored in T00PWM

(T00REG). Subsequently, the match detection is executed using a new set value.

When a read instruction is executed on T00PWM (T00REG), the value in the double buffer

(the last set value) is read out, not the T00PWM (T00REG) value (the currently effective

value).

When a write instruction is executed on T00PWM (T00REG) while the timer is stopped, the

set value is immediately stored in both the double buffer and T00PWM (T00REG).

• When the double buffer is disabled

When a write instruction is executed on T00PWM (T00REG) during the timer operation, the

set value is immediately stored in T00PWM (T00REG). Subsequently, the match detection is

executed using a new set value. If the value set to T00PWM (T00REG) is smaller than the up

counter value, the PPG0 pin is not reversed until the up counter overflows and a match detection

is executed using a new set value. If the value set to T00PWM (T00REG) is equal to the up

counter value, the match detection is executed immediately after data is written into T00PWM

(T00REG). Therefore, the timing of changing the PPG0 pin may not be an integral multiple of

the source clock (Figure 14-10). If these are problems, enable the double buffer.

When a write instruction is executed on T00PWM (T00REG) while the timer is stopped, the

set value is immediately stored in T00PWM (T00REG).

(Example)

Operate TC00 in the 8-bit PPG mode with the operation clock of fcgck/2 and output the 8

µs duty pulse in 32µs cycles (fcgck

= 8 MHz)

SET

(P7FC).0

; Sets P7FC0 to "1"

SET

(P7CR).0

; Sets P7CR0 to "1"

(POFFCR0),0x10

; Sets TC001EN to "1"

; Sets the interrupt master enable flag to "disable"

SET

(EIRH).4

; Sets the INTTC00 interrupt enable register to "1"

; Sets the interrupt master enable flag to "enable"

(T00MOD),0xF3

; Selects the 8-bit PPG mode and fcgck/2

(T00REG),0x80

; Sets the timer register (cycle)

; 32

µs / (2/fcgck) = 0x80

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