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TMP89FS60 Datasheet(PDF) 201 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 201 Page - Toshiba Semiconductor |
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201 / 410 page ![]() Page 187 TMP89FS60 RA002 Figure 14-9 8-bit PPG Mode Timing Chart Figure 14-10 Operation When T00PWM (T00REG) and the Up Counter Have the Same Value LD (T00PWM),0x20 ; Sets the timer register (duty pulse) ; 8 µs / (2/fcgck) = 0x20 SET (T001CR).0 ; Starts TC00 Source clock Counter Timer start 1 0 m m m (Duty pulse) p (1 cycle) s (1 cycle) s (1 cycle) w (1 cycle) rt rs Write to T00PWM Double buffer Match detection Write m Write r Write t Becomes the level selected at TFF0 while the timer is stopped Returns to the level selected at TFF0 INTT00 interrupt request 1 m+1 m0 T00PWM T001CR<T00RUN> ps w Write to T00REG Double buffer Write p Write s Write w p Timer stop Match detection r+1 r 1 0 s r+1 r 1 0 s t+1 t 1 00 w Match detection Match detection Counter clear Counter clear Counter clear Counter clear T00MOD<TFF0> PPG0 pin output When the double buffer is enabled (T00MOD<DBE0>=”1”) r (Duty pulse) r (Duty pulse) t (Duty pulse) ps w T00REG Match detection Match detection Match detection Source clock Counter n-4 n-5 n-2 n Write to T00PWM (T00REG) Write n-2 PPG0 pin output n-3 n-2 n-1 n T00PWM (T00REG) Match detection T00MOD<DBE0> |
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