TMP89FS60 datasheet(203/410 Pages) TOSHIBA

203 / 410 page

Page 189

TMP89FS60

RA002

If the value set to T01+00REG is smaller than the up counter value, the match detection is

executed using a new set value after the up counter overflows. Therefore, the interrupt request

interval may be longer than the selected time. If the value set to T01+00REG is equal to the up

counter value, the match detection is executed immediately after data is written into

T01+00REG. Therefore, the interrupt request interval may not be an integral multiple of the

source clock. If these are problems, enable the double buffer.

When write instructions are executed on T00REG and T01REG in this order while the timer

is stopped, the set value is immediately stored in T01+00REG.

When a read instruction is executed on T01+00REG, the last value written into T01+00REG is read out,

regardless of the T00MOD<DBE1> setting.

(Example)

Operate TC00 and TC01 in the 16-bit timer mode with the operation clock of fcgck/2 [Hz] and generate interrupts at 96

µs

intervals (fcgck = 8 MHz)

(POFFCR0),0x10

; Sets TC001EN to "1"

; Sets the interrupt master enable flag to "disable"

SET

(EIRH).4

; Sets the INTTC00 interrupt enable register to "1"

; Sets the interrupt master enable flag to "enable"

(T01MOD),0xF0

; Selects the 16-bit timer mode and fcgck/2

(T00REG),0x80

; Sets the timer register (96

µs / (2/fcgck) = 0x180)

(T01REG),0x01

; Sets the timer register

(T001CR),0x06

; Starts TC00 and TC001 (16-bit mode)

TMP89FS60 Datasheet(PDF) 203 Page - Toshiba Semiconductor