TMP89FS60 datasheet(208/410 Pages) TOSHIBA

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Page 194

14. 8-bit Timer Counter (TC0)

TMP89FS60

RA002

14.4.7 12-bit pulse width modulation (PWM) output mode

In the 12-bit PWM output mode, TC00 and TC01 are cascaded to output the pulse-width modulated pulses

with a resolution of 8 bits. An additional pulse of 4 bits can be inserted, which enables PWM output with a res-

olution nearly equivalent to 12 bits.

14.4.7.1 Setting

Setting T001CR<TCAS> to "1" connects TC00 and TC01 and activates the 16-bit timer mode. All the

settings of TC00 are ignored and those of TC01 are effective in the 16-bit timer mode.

The 12-bit PWM mode is selected by setting T01MOD<TCM1> to "10". To use the internal clock as the

source clock, set T01MOD<EIN1> to "0" and select the clock at T01MOD<TCK1>. To use an external

clock as the source clock, set T01MOD<EIN1> to "1".

Set T01MOD<DBE1> to "1" to use the double buffer.

Setting T001CR<T01RUN> to "1" starts the operation. After the timer is started, writing to T01MOD

becomes invalid. Be sure to complete the required mode settings before starting the timer. (Make settings

when T001CR<T00RUN> and <T01RUN> are "0".)

Set the count value to be used for the match detection and the additional pulse value as a 12-bit value at

the timer registers T00PWM and T01PWM. Set bits 11 to 8 of the 12-bit value at the lower 4 bits of

T01PWM and set bits 7 to 0 at T00PWM. Refer to the following table for the register configuration. Here-

inafter, the 12-bit value specified by the combined setting of T00PWM and T01PWM is indicated as

T01+00PWM. The timer register settings are reflected on the double buffer or T01+00PWM when a write

instruction is executed on T01PWM. Be sure to execute the write instructions on T00PWM and T01PWM

in this order. (When data is written to the high-order register, the set values of the low-order and high-

order registers become effective at the same time.)

Bits 7 to 4 of T01PWM are not used in the 12-bit PWM mode. However, data can be written to these

bits of T01PWM and the written values are read out as they are when the bits are read. Normally, set these

bits to "0".

PWMDUTYH and PWMDUTYL are 4-bit registers. They are combined to set an 8-bit value of duty

pulse width (time before the first change in the output) for one cycle (256 counts of the source clock).

Hereinafter, an 8-bit value specified by the combined setting of PWMDUTYH and PWMDUTYL is indi-

cated as PWMDUTY.

PWMAD3 to 0 are the additional pulse setting register. Additional pulses can be inserted in specific

cycles of the duty pulse by setting each bit to "1". The additional pulses are inserted in the positions listed

in Table 14-10. PWMAD 3 to 0 can be combined to specify the number of times of inserting the additional

pulses in 16 cycles to any number from 1 to 16. Examples of inserting additional pulses are shown in Fig-

ure 14-13.

Timer register 00

T00PWM

76543

210

(0x0028)

Bit Symbol

PWMDUTYL

PWMAD3

PWMAD2

PWMAD1

PWMAD0

Read/Write

R/W

After reset

11111

111

Timer register 01

T01PWM

76543

210

(0x0029)

Bit Symbol

PWMDUTYH

Read/Write

R/W

After reset

11111

111

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