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TMP89FS60 Datasheet(PDF) 210 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 210 Page - Toshiba Semiconductor |
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210 / 410 page ![]() Page 196 14. 8-bit Timer Counter (TC0) TMP89FS60 RA002 Figure 14-13 Examples of Inserting Additional Pulses 14.4.7.2 Operations Setting T001CR<T01RUN> to "1" allows the up counter to increment based on the selected source clock. When a match between the lower 8 bits of the up counter value and the value set to PWMDUTY is detected, the output of the PWM1 pin is reversed. When T01MOD<TFF1> is "0", the PWM1 pin changes from the "L" to "H" level. When T01MOD<TFF1> is "1", the PWM1 pin changes from the "H" to "L" level. If any of PWMAD3 to 0 is "1", an additional pulse that corresponds to 1 count of the source clock is inserted in specific cycles of the duty pulse. In other words, the PWM1 pin output is reversed at the timing of PWMDUTY+1. When T00MOD<TFF0> is "0", the period of the "L" level becomes longer than the value set to PWMDUTY by 1 source clock. When T00MOD<TFF0> is "1", the period of the "H" level becomes longer than the value set to PWMDUTY by 1 source clock. This function allows 16 cycles of output pulses to be handled with a resolution nearly equivalent to 12 bits. No additional pulse is inserted when PWMAD3 to 0 are all "0". Subsequently, the up counter continues counting up. When the up counter value reaches 256, an over- flow occurs and the up counter is cleared to "0x00". At the same time, the output of the PWM1 pin is reversed. When T01MOD<TFF1> is "0", the PWM1 pin changes from the "H" to "L" level. When T01MOD<TFF1> is "1", the PWM1 pin changes from the "L" to "H" level. At this time, an INTT00 inter- Timer start Additional pulse 123456789 10 11 12 13 14 15 16 17 PWM1 pin output (TFF1=“1”) Timer stop Timer stop PWM1 pin output (TFF1=“0”) INTT00 interrupt request INTT01 interrupt request Cycle When PWMAD1=“1” Additional pulse Timer start 123456789 10 11 12 13 14 15 16 17 PWM1 pin output (TFF1=“1”) PWM1 pin output (TFF1=“0”) INTT00 interrupt request INTT01 interrupt request Cycle When PWMAD0 = “1” and PWMAD2 = “1” Additional pulse Additional pulse Additional pulse Additional pulse Additional pulse |
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