TMP89FS60 datasheet(211/410 Pages) TOSHIBA

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TMP89FS60

RA002

rupt request is generated (an INTT00 interrupt request is generated each time an overflow occurs.) An

INTT01 interrupt request is generated at the 16

× n-th overflow (n=1, 2, 3...). Subsequently, the up counter

continues counting up.

When T001CR<T01RUN> is set to "0" during the timer operation, the up counter is stopped and

cleared to "0x00". The PWM1 pin returns to the level selected at T01MOD<TFF1>.

When an external source clock is selected, input the clock at the TC00 pin. The maximum frequency to

be supplied is fcgck/2 [Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/24 [Hz] (in SLOW1/2 or SLEEP1

mode), and a pulse width of two machine cycles or more is required at both the "H" and "L" levels.

Figure 14-14 PWM1 Pin Output

14.4.7.3 Double buffer

The double buffer can be used for T01+00PWM by setting T01MOD<DBE1>. The double buffer is dis-

abled by setting T01MOD<DBE1> to "0" or enabled by setting T01MOD<DBE1> to "1".

• When the double buffer is enabled

When write instructions are executed on T00PWM and T01PWM in this order during the

timer operation, the set value is first stored in the double buffer, and T01+00PWM is not

updated immediately. T01+00PWM compares the previous set value with the up counter value.

When the 16

× n-th overflow occurs, an INTT01 interrupt request is generated and the double

buffer set value is stored in T01+00PWM. Subsequently, the match detection is executed using

a new set value.

When a read instruction is executed on T01+00PWM (T00REG), the value in the double

buffer (the last set value) is read out, not the T01+00PWM value (the currently effective value).

When write instructions are executed on T00PWM and T01PWM in this order while the

timer is stopped, the set value is immediately stored in both the double buffer and

T01+00PWM.

• When the double buffer is disabled

When write instructions are executed on T00PWM and T01PWM in this order during the

timer operation, the set value is immediately stored in T01+00PWM. Subsequently, the match

detection is executed using a new set value. If the value set to T01+00PWM is smaller than the

up counter value, the PWM1 pin is not reversed until the up counter overflows and a match

detection is executed using a new set value. If the value set to T01+00PWM is equal to the up

counter value, the match detection is executed immediately after data is written into

T01+00PWM. Therefore, the timing of changing the PWM1 pin may not be an integral multiple

of the source clock. Similarly, if T01+00PWM is set during the additional pulse output, the tim-

ing of changing the PWM1 pin may not be an integral multiple of the source clock. If these are

problems, enable the double buffer.

PWMDUTY

Timer start

Additional

pulse

(1 source clock)

(Duty pulse

width)

256 counts

(cycle width)

256 counts

(cycle width)

PWM1 pin output

(TFF0=“1”)

PWMDUTY

(Duty pulse

width)

PWM1 pin output

(TFF0=“0”)

TMP89FS60 Datasheet(PDF) 211 Page - Toshiba Semiconductor

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