TMP89FS60 datasheet(215/410 Pages) TOSHIBA

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Page 201

TMP89FS60

RA002

When an external source clock is selected, input the clock at the TC00 pin. The maximum frequency to

be supplied is fcgck/2 [Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/24 [Hz] (in SLOW1/2 or SLEEP1

mode), and a pulse width of two machine cycles or more is required at both the "H" and "L" levels.

14.4.8.3 Double buffer

The double buffer can be used for T01+00PWM and T01+00REG by setting T01MOD<DBE1>. The

double buffer is enabled by setting T01MOD<DBE1> to "0" or disabled by setting T01MOD<DBE1> to

"1".

• When the double buffer is enabled

When a write instruction is executed on T01PWM after write instructions are executed on

T00REG, T01REG and T00PWM during the timer operation, the set values are first stored in

the double buffer, and T01+00PWM and T01+00REG are not updated immediately.

T01+00PWM and T01+00REG compare the previous set values with the up counter value.

When a match between the up counter value and the T01+00REG set value is detected, an

INTT01 interrupt request is generated and the double buffer set values are stored in

T01+00PWM and T01+00REG. Subsequently, the match detection is executed using new set

values.

When a write instruction is executed on T01PWM after write instructions are executed on

T00REG, T01REG and T00PWM while the timer is stopped, the set values are immediately

stored in both the double buffer and T01+00PWM and T01+00REG.

• When the double buffer is disabled

When a write instruction is executed on T01PWM after write instructions are executed on

T00REG, T01REG and T00PWM during the timer operation, the set values are immediately

stored in T01+00PWM and T01+00REG. Subsequently, the match detection is executed using

new set values.

If the value set to T01+00PWM or T01+00REG is smaller than the up counter value, the

PPG1

pin is not reversed until the up counter overflows and a match detection is executed using

a new set value. If the value set to T01+00PWM or T01+00REG is equal to the up counter

value, the match detection is executed immediately after data is written into T01+00PWM and

T01+00REG. Therefore, the timing of changing the PPG1 pin may not be an integral multiple of

the source clock. If these are problems, enable the double buffer.

When a write instruction is executed on T01PWM after write instructions are executed on

T00REG, T01REG and T00PWM while the timer is stopped, the set values are immediately

stored in T01+00PWM and T01+00REG.

When read instructions are executed on T01+00PWM and T01+00REG, the last value written into

T01+00REG is read out, regardless of the T00MOD<DBE1> setting.

(Example)

Operate TC00 and TC01 in the 16-bit PPG mode with the operation clock of fcgck/2 and output the 68

µs duty pulse in 96µs

cycles (fcgck = 8 MHz)

SET

(P7FC).1

; Sets P7FC0 to "1"

SET

(P7CR).1

; Sets P7CR0 to "1"

(POFFCR0),0x10

; Sets TC001EN to "1"

; Sets the interrupt master enable flag to "disable"

SET

(EIRH).4

; Sets the INTTC00 interrupt enable register to "1"

; Sets the interrupt master enable flag to "enable"

(T01MOD),0xF3

; Selects the 8-bit PPG mode and fcgck/2

(T00REG),0x80

; Sets the timer register (cycle)

(T01REG),0x01

; Sets the timer register (cycle)

; 96

µs / (2/fcgck) = 0x0180

(T00PWM),0x10

; Sets the timer register (duty pulse)

(T01PWM),0x01

; Sets the timer register (duty pulse)

; 68

µs / (2/fcgck) = 0x0110

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