TMP89FS60 datasheet(212/410 Pages) TOSHIBA

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Page 198

14. 8-bit Timer Counter (TC0)

TMP89FS60

RA002

When write instructions are executed on T00PWM and T01PWM in this order while the

timer is stopped, the set value is immediately stored in T01+00PWM.

Figure 14-15 12-bit PWM Mode Timing Chart

(Example)

Operate TC00 and TC01 in the 12-bit PWM mode with the operation clock of fcgck/2 and output a duty pulse nearly equiva-

lent to 14.0625

µs in 64µs cycles (fcgck = 8 MHz)

(Actually, output a duty pulse of 225

µs in total in 16 cycles (1024 µs))

SET

(P7FC).1

; Sets P7FC1 to "1"

SET

(P7CR).1

; Sets P7CR1 to "1"

(POFFCR0),0x10

; Sets TC001EN to "1"

; Sets the interrupt master enable flag to "disable"

SET

(EIRH).4

; Sets the INTTC00 interrupt enable register to "1"

; Sets the interrupt master enable flag to "enable"

(T01MOD),0xF2

; Selects the 16-bit PWM mode and fcgck/2

(T00PWM),0x84

; Sets the timer register (duty pulse)

; (14.0625

µs × 16) / (2/fcgck) = 0x384

(T00PWM),0x03

; Sets the timer register (duty pulse)

(T001CR),0x06

; Starts TC00 and TC01

Source clock

Counter

Timer start

km (0001)

(Duty pulse)

256 counts

(Cycle 1)

256 counts

(Cycle 2)

256 counts

(Cycle 9)

256 counts

(Cycle 16)

(Cycle 17)

rs (0011)

Write to T00PWM

Double buffer

Match detection

Write m (0001)

Write s (0011)

Becomes the level selected at

TFF0 while the timer is stopped

Interrupt request

Interrupt reques

Interrupt request

Write to T01PWM

Write k

Write r

INTT00 interrupt request

0001

0011

PWMDUTY

PWMAD3 ~ 0

T001CR<T00RUN>

256

Match detection

256

Match detection

Counter

clear

Overflow

Counter

clear

Counter

clear

Counter

clear

T00MOD<TFF0>

PWM0 pin output

When the double buffer is enabled (T01MOD<DBE1>=”1”)

(Duty pulse)

km+1

(Duty pulse)

Additional pulse

Interrupt request

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