TMP89FS60 datasheet(264/410 Pages) TOSHIBA

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17. Synchronous Serial Interface (SIO)

17.5 Transfer Modes

TMP89FS60

RA001

17.5.2 8-bit Receive Mode

The 8-bit receive mode is selected by setting SIO0CR<SIOM> to "10".

17.5.2.1 Setting

As in the case of the transmit mode, before starting the receive operation, select the transfer edges at

SIO0CR<SIOEDG>, a transfer format at SIO0CR<SIODIR> and a serial clock at SIO0CR<SIOCKS>.

To use the internal clock as the serial clock, select an appropriate serial clock at SIO0CR<SIOCKS>. To

use an external clock as the serial clock, set SIO0CR<SIOCKS> to "111".

The 8-bit receive mode is selected by setting SIO0CR<SIOM> to "10".

Reception is started by setting SIO0CR<SIOS> to "1".

Writing data to SIO0CR<SIOEDG, SIOCKS and SIODIR> is invalid when the serial communication is

in progress, or when SIO0SR<SIOF> is "1". Make these settings while the serial communication is

stopped. While the serial communication is in progress (SIO0SR<SIOF>="1"), only writing "00" to

SIO0CR<SIOM> or writing "0" to SIO0CR<SIOS> is valid.

17.5.2.2 Starting the receive operation

Reception is started by setting SIO0CR<SIOS> to "1". External serial data is taken into the shift register

from the SI0 pin according to the settings of SIO0CR<SIOEDG, SIOCKS and SIODIR>.

In the internal clock operation, the serial clock of the selected baud rate is output from the SCLK0 pin.

In the external clock operation, an external clock must be supplied to the SCLK0 pin.

By setting SIO0CR<SIOS> to "1", SIO0SR<SIOF and SEF> are automatically set to "1".

17.5.2.3 Operation on completion of reception

When the data reception is completed, the data is transferred from the shift register to SIO0BUF and an

INTSIO0 interrupt request is generated. The receive completion flag SIO0SR<REND> is set to "1".

In the operation with the internal clock, the serial clock output is stopped until the receive data is read

from SIO0BUF (automatic wait). At this time, SIO0SR<SEF> is set to "0". By reading the receive data

from SIO0BUF, SIO0SR<SEF> is set to "1", the serial clock output is restarted and the receive operation

continues.

In the operation with an external clock, data can be continuously received without reading the received

data from SIO0BUF. In this case, data must be read from SIO0BUF before the subsequent data has been

fully received. If the subsequent data is received completely before reading data from SIO0BUF, the over-

run error flag SIO0SR<OERR> is set to "1". When an overrun error has occurred, set SIO0CR<SIOM> to

"00" to abort the receive operation. The data received at the occurrence of an overrun error is discarded,

and SIO0BUF holds the data value received before the occurrence of the overrun error.

SIO0SR<REND> is cleared to "0" by reading data from SIO0BUF. SIO0SR<OERR> is cleared by

reading SIO0SR.

17.5.2.4 Stopping the receive operation

Set SIO0CR<SIOS> to "0" to stop the receive operation. When SIO0SR<SEF> is "0", or when the shift

operation is not in progress, the operation is stopped immediately. Unlike the transmit mode, no INTSIO0

interrupt request is generated in this state.

When SIO0SR<SEF> is "1", the operation is stopped after the 8-bit data has been completely received

(reserved stop). At this time, an INTSIO0 interrupt request is generated.

TMP89FS60 Datasheet(PDF) 264 Page - Toshiba Semiconductor

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