TMP89FS60 datasheet(261/410 Pages) TOSHIBA

261 / 410 page

Page 247

TMP89FS60

RA001

Figure 17-3 8-bit Transmit Mode (Internal Clock and Reserved Stop)

Figure 17-4 8-bit Transmit Mode (Internal Clock and Forced Stop)

SO0 pin (output)

Internal clock

SCLK0 pin (output)

INTSIO0 interrupt request

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Write to SIO0BUF

SIO0BUF

SIO0CR<SIOS>

SIO0CR<SIOM>

SIO0SR<SIOF>

SIO0SR<SEF>

SIO0SR<TBFL>

Data A

Data B

Writing data A

Writing data B

Writing data C

Reserved stop

Start operation

An interrupt is generated

after transmission in

case of reserved stop

The level is held for the period

of the internal clock×(1/2)

Automatic wait

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Data C

SO0 pin (output)

Internal clock

SCLK0 pin (output)

INTSIO0 interrupt request

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2

Write to SIO0BUF

SIO0BUF

SIO0CR<SIOS>

SIO0CR<SIOM>

SIO0SR<SIOF>

SIO0SR<SEF>

SIO0SR<TBFL>

Data A

Data B

Writing data A

Writing data B

Writing data C

Writing data D

Forced stop

Start operation

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5

Data C

Forced stop

Forced stop has priority

over reserved stop

Data is not held but

becomes the H level

Clock output is stopped

Reserved stop

TMP89FS60 Datasheet(PDF) 261 Page - Toshiba Semiconductor

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