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TMP89FS60 Datasheet(PDF) 258 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 258 Page - Toshiba Semiconductor |
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258 / 410 page  Page 244 17. Synchronous Serial Interface (SIO) 17.4 Functions TMP89FS60 RA001 Figure 17-2 Transfer Edge Note:When an external clock input is used, 4/fcgck or longer is needed between the receive edge at the 8th bit and the transfer edge at the first bit of the next transfer. R1 R0 R2 R3 R4 R5 R6 R7 T1 T0 T2 T3 T4 T5 T6 T7 SLCK0 pin SO0 pin SI0 pin When SIOCR<SIOEDG>=“0” R1 R0 R2 R3 R4 R5 R6 R7 T1 T0 T2 T3 T4 T5 T6 T7 SCLK0 pin SO0 pin SI0 pin When SIOCR<SIOEDG>=“1” C7 C6 D0 D1 D2 A7 A6 B0 B1 B2 tBI Leading edge at the 1st bit (transmit edge) Trailing edge at the 8th bit (receive edge) SCLK0 pin SO0 pin SI0 pin Symbol Name Minimum time tBI Interval time between bytes 4/fcgck |
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