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TMP89FS60 Datasheet(PDF) 265 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 265 Page - Toshiba Semiconductor |
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265 / 410 page  Page 251 TMP89FS60 RA001 After the operation has stopped completely, SIO0SR<SIOF and SEF> are cleared to "0". Other SIO0SR registers keep their values. The receive operation can be forced to stop by setting SIO0CR<SIOM> to "00" during the operation. By setting SIO0CR<SIOM> to "00", SIO0CR<SIOS> and SIO0SR are cleared to "0" and the SIO stops the operation, regardless of the SIO0SR<SEF> value. If the internal clock is selected, the SCLK0 pin returns to the initial level. Figure 17-8 8-bit Receive Mode (Internal Clock and Reserved Stop) SI0 pin (input) Internal clock SCLK0 pin (output) INTSIO0 interrupt request Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Read SIO0BUF SIO0BUF AC SIO0CR<SIOS> SIO0SR<SIOF> SIO0SR<SEF> SIO0SR<REND> Data A Reading data A Reading data C Reserved stop Automatic wait Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Data C SIO0CR<SIOM> 10 |
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