R7F100LLL3CFB datasheet(131/148 Pages) RENESAS

131 / 148 page

RL78/L23

2. Electrical Characteristics

R01DS0502EJ0110 Rev.1.10

Page 131 of 145

Oct 31, 2025

3. 1/4 bias method, VDD reference (MDSET2 to MDSET0 = 010B, LBAS1 to LBAS0 = 10B)

Note 1.

C1 to C5 are the capacitors that are to be connected to the LCD drive voltage pins of the MCU.

C1 is to be connected between CAPH and CAPL.

C2 is to be connected between VL1 and GND.

C3 is to be connected between VL2 and GND.

C4 is to be connected between VL3 and GND. This is required when the voltage generation method is switched to the

internal voltage boosting method.

C5 is to be connected between VL4 and GND.

C1 = C2 = C3 = C4 = C5 = 0.47 µF ±30%

Note 2.

This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).

(TA = -40 to +105°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Item

Symbols

Conditions

Min.

Typ.

Max.

Unit

VL4 output voltage

VL4

C1 to C5 = 0.47 µFNote 1

VDD

VL3 output voltage

VL3

C1 to C5 = 0.47 µFNote 1

3/4VL4

-3%

3/4VL4

+3%

VL2 output voltage

VL2

C1 to C5 = 0.47 µFNote 1

1/2VL4

-3%

1/2VL4

+3%

VL1 output voltage

VL1

C1 to C5 = 0.47 µFNote 1

1/4VL4

-3%

1/4VL4

+3%

Capacitor split wait timeNote 2

tVWAIT

100

R7F100LLL3CFB Datasheet(PDF) 131 Page - Renesas Technology Corp

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