TLE8262E datasheet(56/93 Pages) INFINEON

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Data Sheet

Rev. 1.0, 2009-03-31

TLE8262E

Supervision Functions

11.2.1

Time-out Watchdog

The Time-out Watchdog is an easier and less secure type of watchdog. Compared to the Window Watchdog there

is no closed window existing. The watchdog trigger can be done any time within the watchdog time.

A watchdog trigger is detected as a write access to the “WD Refresh” within the SPI control word. The bit needs

to be toggle (transition HIGH to LOW or LOW to HIGH) within the watchdog window. The trigger is accepted when

the CSN input becomes HIGH.

A correct watchdog trigger starts a new window. The period is selected via the Window Watchdog timing bit field

in the range of 16 ms to 1024 ms. For the safe trigger area the tolerance of the oscillator has to be taken into

consideration, so the safe trigger time is below 90% of the programmed Watchdog time. It is possible to refresh

the Watchdog with any SPI programming with the mode selection Normal, Stop, SW Flash or Read Only.

Should the trigger signal not meet the window, depending on the configuration, the SBC will go to SBC Restart

Mode or to Fail-Safe Mode. A watchdog reset is created by setting the reset output RO low. In config 1 and config

3 the watchdog starts again in Normal Mode with the default watchdog setting (256ms Time-out Watchdog). The

watchdog failure can be read at the bits RM0, RM1, LH0, LH1, LH2 via SPI.

11.2.2

Window Watchdog

A Watchdog trigger is detected as a write access to the “WD Refresh” within the SPI control word. The bit needs

to be toggle (transition HIGH to LOW or LOW to HIGH) in the open window. The trigger is accepted when the CSN

input becomes HIGH.

A correct Watchdog trigger results in starting the Window Watchdog by a closed window with a width of typically

50% of the selected Window Watchdog reset period. This period, selected via the Window Watchdog timing bit

field, is in the range of 16 ms to 1024 ms. This closed window is followed by an open window, with a width of typical

50% of the selected period. From now on, the microcontroller must serve the Watchdog by periodically toggling

the Watchdog bit. This bit toggling access must meet the open window. The tolerance of the oscillator has to be

taken into consideration, so the safe window to trigger the Watchdog is from 55% to 90% of the programmed

Window Watchdog time. It is possible to refresh the Watchdog with any SPI programming with the mode selection

Normal, Stop, SW Flash or Read Only. A correct Watchdog service immediately results in starting the next closed

window (see Figure 23, safe trigger area).

Should the trigger signal not meet the open window, depending on the configuration the SBC will go to SBC

Restart Mode or to Fail-Safe Mode. A watchdog reset is created by setting the reset output RO low (see

Figure 24). In config 1 and config 3 the watchdog starts again in Normal Mode with the default watchdog setting

(256ms Time-out Watchdog). The watchdog failure can be read at the bits RM0, RM1, LH0, LH1, LH2 via SPI.

TLE8262E Datasheet(PDF) 56 Page - Infineon Technologies AG