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TLE8262E Datasheet(PDF) 71 Page - Infineon Technologies AG |
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TLE8262E Datasheet(HTML) 71 Page - Infineon Technologies AG |
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71 / 93 page ![]() Data Sheet 71 Rev. 1.0, 2009-03-31 TLE8262E Serial Peripheral Interface 15 Serial Peripheral Interface 15.1 SPI Description The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK supplied by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 34). The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After the CSN input returns from LOW to HIGH, the word that has been read in becomes the new control word. The SDO output switches to tri-state status (high impedance) at this point, thereby releasing the SDO bus for other use. The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is shifted out of the output register after every rising edge on CLK. The number of received input clocks is supervised by a modulo-16 operation and the Input / Control Word is discarded in case of a mismatch. This error is flagged in the following SPI output by a “HIGH” at the data output (SDO pin, bit FO) before the first rising edge of the clock is received. The SPI of the SBC is not daisy chain capable. Figure 34 SPI Data Transfer Timing 15.2 Corrupted data in the SPI data input When the microcontroller send a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI command can be either a number of bits different of 16, the mode selection (MS2..0) = 000 or requesting to go to an SBC mode which is not allowed by the state machine, for example from SBC Stop Mode to SBC SW Flash Mode. In that case, an interrupt is generated (if not inhibited) and the bit SPI Fail is set. Since the SPI data is corrupted, the next SPI output data will remain the former one (the information is then repeated). 0 0 + 1 2 3 4 5 6 7 8 9 10 15 1 + 0 1 2 3 4 5 6 11 12 13 14 7 8 9 10 15 FI FI - CSN high to low: SDO is enabled. Status information transferred to output shift register CSN low to high: data from shift register is transferred to output functions SDI: will accept data on the falling edge of CLK signal SDO: will change state on the rising edge of CLK signal Actual status 11 12 13 14 Actual data New data New status SDO SDI CSN CLK time time time time FO FO - 0 + 1 + |
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