AT89LP6440 datasheet(17/194 Pages) ATMEL

17 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

Figure 3-8 shows a hardware configuration for accessing 256-byte blocks of external RAM using

an 8-bit paged address. Port 0 serves as a multiplexed address/data bus to the RAM. The ALE

strobe is used to latch the address byte into an external register so that Port 0 can be freed for

data input/output. The Port 2 I/O lines (or other ports) can provide control lines to page the mem-

ory; however, this operation is not handled automatically by hardware. The software application

must change the Port 2 register when appropriate to access different pages. The MOVX @Ri

instructions use Paged Address mode.

Figure 3-8.

External Memory 8-bit Paged Address Mode

Note that prior to using the external memory interface, Port 2, WR (P3.6), RD (P3.7) and ALE

(P4.4) must be configured as outputs. See Section 10.1 “Port Configuration” on page 44. Port 0

is configured automatically to push-pull output mode when outputting address or data and is

I/O

ALE

AT89LP

DATA

LATCH

EXTERNAL

DATA

MEMORY

ADDR

PAGE

BITS

Table 3-4.

AUXR

– Auxiliary Control Register

CLKREG = 8EH

Reset Value = xxx0 0000B

Not Bit Addressable

––

–

XSTK

WS1WS0

EXRAM

ALES

Bit

543

Symbol

Function

XSTK

Extended Stack Enable. When XSTK = 0 the stack resides in IDATA and is limited to 256 bytes. Set XSTK = 1 to place

the stack in EDATA for up to 4K bytes of extended stack space. All PUSH, POP, CALL and RET instructions will incur a

one or two cycle penalty when accessing the extended stack.

WS[1-0]

Wait State Select. Determines the number of wait states inserted into external memory accesses.

WS1

WS0

Wait States

RD / WR Strobe Width

000

1 x tCYC

011

2 x t

CYC

102

3 x tCYC

113

4 x tCYC

EXRAM

External RAM Enable. When EXRAM = 0, MOVX instructions can access the internally mapped portions of the address

space. Accesses to addresses above internally mapped memory will access external memory. Set EXRAM = 1 to

bypass the internal memory and map the entire address space to external memory.

ALES

ALE Idle State. When ALES = 0 the idle polarity of ALE is high (active). When ALES = 1 the idle polarity of ALE is low

(inactive). The ALE strobe pulse is always active high. ALES must be zero in order to use P4.4 as a general I/O.

AT89LP6440 Datasheet(PDF) 17 Page - ATMEL Corporation

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