AT89LP6440 datasheet(99/194 Pages) ATMEL

99 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

Figure 17-2. SPI Master-Slave Interconnection

When the SPI is configured as a Master (MSTR in SPCR is set), the operation of the SS pin

depends on the setting of the Slave Select Ignore bit, SSIG. If SSIG = 1, the SS pin is a general

purpose output pin which does not affect the SPI system. Typically, the pin will be driving the SS

pin of an SPI Slave. If SSIG = 0, SS must be held high to ensure Master SPI operation. If the SS

pin is driven low by peripheral circuitry when the SPI is configured as a Master with SSIG = 0,

the SPI system interprets this as another master selecting the SPI as a slave and starting to

send data to it. To avoid bus contention, the SPI system takes the following actions:

The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of

the SPI becoming a Slave, the MOSI and SCK pins become inputs.

The MODF Flag in SPSR is set, and if the SPI interrupt is enabled, the interrupt routine

will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-

bility that SS may be driven low, the interrupt should always check that the MSTR bit is still set. If

the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI

Master mode.

17.1

Master Operation

An SPI master device initiates all data transfers on the SPI bus. The AT89LP6440 is configured

for master operation by setting MSTR = 1 in SPCR. Writing to the SPI data register (SPDR)

while in master mode loads the transmit buffer. If the SPI shift register is empty, the byte in the

transmit buffer is moved to the shift register; the transmit buffer empty flag, TXE, is set; and a

transmission begins. The transfer may start after an initial delay, while the clock generator waits

for the next full bit slot of the specified baud rate. The master shifts the data out serially on the

MOSI line while providing the serial shift clock on SCK. When the transfer finishes, the SPIF flag

is set to “1” and an interrupt request is generated, if enabled. The data received from the

addressed SPI slave device is also transferred from the shift register to the receive buffer.

Therefore, the SPIF bit flags both the transmit-complete and receive-data-ready conditions. The

received data is accessed by reading SPDR.

While the TXE flag is set, the transmit buffer is empty. TXE can be cleared by software or by

writing to SPDR. Writing to SPDR will clear TXE and load the transmit buffer. The user may load

the buffer while the shift register is busy, i.e. before the current transfer completes. When the

current transfer completes, the queued byte in the transmit buffer is moved to the shift register

and the next transfer commences. TXE will generate an interrupt if the SPI interrupt is enabled

8-Bit Shift Register

Master

Slave

MSB

LSB

MSB

LSB

8-Bit Shift Register

MISO

DISSO

SSIG

MOSI

GPIO

SSIG

VCC

SCK

MODF

Clock

Generator

AT89LP6440 Datasheet(PDF) 99 Page - ATMEL Corporation

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