AT89LP6440 datasheet(18/194 Pages) ATMEL

18 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

automatically tristated when inputting data regardless of the Port 0 configuration. The Port 0

configuration will determine the idle state of Port 0 when not accessing the external memory.

Figure 3-9 and Figure 3-10 show examples of external data memory write and read cycles,

respectively. The address on P0 and P2 is stable at the falling edge of ALE. The idle polarity of

ALE is controlled by ALES (AUXR.0). When ALES = 0 the idle polarity of ALE is high (active).

When ALES = 1 the idle polarity of ALE is low (inactive). The ALE strobe pulse is always active

high. Unlike standard 8051s, ALE will not toggle continuously when not accessing external

memory. ALES must be zero in order to use P4.4 as a general-purpose I/O. The WS bits in

AUXR can extended the RD and WR strobes by 1, 2 or 3 cycles as shown in Figures 3-11, 3-12

and 3-13. If a longer strobe is required, the application can scale the system clock with the clock

divider to meet the requirements (See Section 6.5 on page 31).

Figure 3-9.

External Data Memory Write Cycle (WS =00B)

Figure 3-10. External Data Memory Read Cycle (WS = 00B)

CLK

ALE

ALES = 0

ALES = 1

DPL or Ri OUT

P0 SFR

P2 SFR

DPH or P2 OUT

DATA OUT

CLK

ALE

ALES = 0

ALES = 1

FLOAT

DATA SAMPLED

DPL or Ri OUT

P0 SFR

P2 SFR

DPH or P2 OUT

AT89LP6440 Datasheet(PDF) 18 Page - ATMEL Corporation