AT89LP6440 datasheet(4/194 Pages) ATMEL

4 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

1.5

Pin Description

Table 1-1.

AT89LP6440 Pin Description

Pin Number

Symbol

Type

Description

TQFP

PLCC

PDIP

VQFN

1761

P1.5

I/O

P1.5: User-configurable I/O Port 1 bit 5.

MOSI: SPI master-out/slave-in. When configured as master, this pin is an output.

When configured as slave, this pin is an input.

GPI5: General-purpose Interrupt input 5.

P1.6

I/O

P1.6: User-configurable I/O Port 1 bit 6.

MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When

configured as slave, this pin is an output.

GPI6: General-purpose Interrupt input 6.

3P1.7

I/O

P1.7: User-configurable I/O Port 1 bit 7.

SCK: SPI Clock. When configured as master, this pin is an output. When configured

as slave, this pin is an input.

GPI7: General-purpose Interrupt input 7.

4109

P4.2

I/O

P4.2: User-configurable I/O Port 4 bit 2 (if Reset Fuse is disabled).

RST: External Active-Low Reset input (if Reset Fuse is enabled. See “External

Reset” on page 34.).

DCL: Serial Clock input for On-Chip Debug Interface when OCD is enabled.

511

105

P3.0

I/O

P3.0: User-configurable I/O Port 3 bit 0.

RXD: Serial Port Receiver Input.

612

VDD

Supply Voltage

713

117

P3.1

I/O

P3.1: User-configurable I/O Port 3 bit 1.

TXD: Serial Port Transmitter Output.

P3.2

I/O

P3.2: User-configurable I/O Port 3 bit 2.

INT0: External Interrupt 0 Input or Timer 0 Gate Input.

915

139

P3.3

I/O

P3.3: User-configurable I/O Port 3 bit 3.

INT1: External Interrupt 1 Input or Timer 1 Gate Input

P3.4

I/O

P3.4: User-configurable I/O Port 3 bit 4.

T1: Timer/Counter 0 External input or PWM output.

P3.5

I/O

P3.5: User-configurable I/O Port 3 bit 5.

T1: Timer/Counter 1 External input or PWM output.

P3.6

I/O

P3.6: User-configurable I/O Port 3 bit 6.

WR: External memory interface Write Strobe (active-low).

P3.7

I/O

P3.7: User-configurable I/O Port 3 bit 7.

RD: External memory interface Read Strobe (active-low).

P4.1

I/O

P4.1: User-configurable I/O Port 4 bit 1.

XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the

internal RC oscillator is selected as the clock source.

CLKOUT: When the internal RC oscillator is selected as the clock source, may be

used to output the internal clock divided by 2.

DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and

the external clock is selected as the clock source.

P4.0

I/O

P4.0: User-configurable I/O Port 4 bit 0.

XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits.

It may be used as a port pin if the internal RC oscillator is selected as the clock

source.

DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and

the internal RC oscillator is selected as the clock source.

N/A

GND

Ground

AT89LP6440 Datasheet(PDF) 4 Page - ATMEL Corporation

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