AT89LP6440 datasheet(23/194 Pages) ATMEL

23 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

Figure 5-3.

Two-cycle ALU Operation (Example: ADD A, #data)

5.1

Multiply–Accumulate Unit (MAC)

The AT89LP6440 includes a multiply and accumulate (MAC) unit that can significantly speed up

many mathematical operations required for digital signal processing. The MAC unit includes a

16-by-16 bit multiplier and a 40-bit adder that can perform integer or fractional multiply-accumu-

late operations on signed 16-bit input values. The MAC unit also includes a 1-bit arithmetic

shifter that will left or right shift the contents of the 40-bit MAC accumulator register (M).

A block diagram of the MAC unit is shown in Figure 5-4. The 16-bit signed operands are pro-

vided by the register pairs (AX,ACC) and (BX,B) where AX (E1H) and BX (F7H) hold the higher

order bytes. The 16-by-16 bit multiplication is computed through partial products using the

AT89LP6440’s 8-bit multiplier. The 32-bit signed product is added to the 40-bit M accumulator

All computation is done in signed two’s complement form.

Figure 5-4.

Multiply–Accumulate Unit

System Clock

Total Execution Time

Fetch Immediate Operand

ALU Operation Execute

Result Write Back

Fetch Next Instruction

MAC AB:

AX ACC

}

BX B

{, }

←

ACC

8 x 8-bit Signed MULT

40-bit ADD

Shifter

MACH

MACL

PSW

MRW

SMLA

SMLB

AT89LP6440 Datasheet(PDF) 23 Page - ATMEL Corporation