MC68HC705P9CS datasheet(51/160 Pages) FREESCALE

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Central Processor Unit (CPU)

Instruction Set

MC68HC705P9 — Rev. 4.0

Technical Data

MOTOROLA

Central Processor Unit (CPU)

4.7.1.4 Extended

Extended instructions use three bytes and can access any address in

memory. The first byte is the opcode; the second and third bytes are the

high and low bytes of the operand address.

When using the Motorola assembler, the programmer does not need to

specify whether an instruction is direct or extended. The assembler

automatically selects the shortest form of the instruction.

4.7.1.5 Indexed, No Offset

Indexed instructions with no offset are 1-byte instructions that can

access data with variable addresses within the first 256 memory

locations. The index register contains the low byte of the effective

address of the operand. The CPU automatically uses $00 as the high

byte, so these instructions can address locations $0000–$00FF.

Indexed, no offset instructions are often used to move a pointer through

a table or to hold the address of a frequently used RAM or I/O location.

4.7.1.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are 2-byte instructions that can access

data with variable addresses within the first 511 memory locations. The

CPU adds the unsigned byte in the index register to the unsigned byte

following the opcode. The sum is the effective address of the operand.

These instructions can access locations $0000–$01FE.

Indexed 8-bit offset instructions are useful for selecting the kth element

in an n-element table. The table can begin anywhere within the first 256

memory locations and could extend as far as location 510 ($01FE). The

k value is typically in the index register, and the address of the beginning

of the table is in the byte following the opcode.

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MC68HC705P9CS Datasheet(PDF) 51 Page - Freescale Semiconductor, Inc