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MC68HC705P9CS Datasheet(PDF) 107 Page - Freescale Semiconductor, Inc |
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MC68HC705P9CS Datasheet(HTML) 107 Page - Freescale Semiconductor, Inc |
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107 / 160 page  Timer Timing MC68HC705P9 — Rev. 4.0 Technical Data MOTOROLA Timer 107 Figure 9-8. Output Compare Timing Figure 9-9. Timer Overflow Timing INTERNAL TIMER T00 T01 T10 T11 OUTPUT COMPARE 16-BIT $FFEB $FFED $FFEE $FFEC OUTPUT COMPARE $FFED CPU WRITES $FFED $FFEF FLAG AND TCMP REGISTERS NOTES: 1. A write to the output compare registers may occur at any time, but a compare only occurs at timer state T01. Therefore, the compare may follow the write by up to four cycles. 2. The output compare flag is set at the timer state T11 that follows the comparison latch. BUS CLOCK CLOCKS COUNTER COMPARE REGISTER LATCH $FFFF $0001 $0002 $0000 INTERNAL TIMER T00 T01 T10 T11 OVERFLOW 16-BIT FLAG (TOF) BUS CLOCK CLOCKS COUNTER Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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