MSP430F5632IPZ datasheet(39/101 Pages) TI

39 / 101 page

MSP430F563x

www.ti.com

SLAS650A – JUNE 2010 – REVISED JULY 2010

Recommended Operating Conditions

MIN

NOM

MAX

UNIT

PMMCOREVx = 0

1.8

3.6

Supply voltage during program execution and flash

PMMCOREVx = 0, 1

2.0

3.6

VCC

programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =

PMMCOREVx = 0, 1, 2

2.2

3.6

DVCC = VCC)

(1)

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

PMMCOREVx = 0

1.8

3.6

Supply voltage during USB operation, USB PLL

PMMCOREVx = 0, 1

2.0

3.6

disabled

PMMCOREVx = 0, 1, 2

2.2

3.6

USB_EN = 1, UPLLEN = 0

VCC, USB

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

Supply voltage during USB operation, USB PLL

PMMCOREVx = 2

2.2

3.6

enabled(2)

PMMCOREVx = 2, 3

2.4

3.6

USB_EN = 1, UPLLEN = 1

Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =

VSS

DVSS2 = DVSS3 = VSS)

TA = 0°C to 85°C

1.55

3.6

VBAT,RTC

Backup-supply voltage with RTC operational

TA = –40°C to 85°C

1.70

3.6

VBAT,MEM

Backup-supply voltage with backup memory retained.

TA = –40°C to 85°C

1.20

3.6

Operating free-air temperature

I version

–40

°C

Operating junction temperature

I version

–40

°C

CBAK

Capacitance at pin VBAK

4.7

CVCORE

Capacitor at VCORE

470

CDVCC/CVCORE

Capacitor ratio of DVCC to VCORE

PMMCOREVx = 0,

1.8 V

≤ VCC ≤ 3.6 V

8.0

(default condition)

PMMCOREVx = 1, 2

12.0

Processor frequency (maximum MCLK frequency)(3) (4)

≤ VCC ≤ 3.6 V

fSYSTEM

MHz

(see Figure 1)

PMMCOREVx = 2,

16.0

2.2 V

≤ VCC ≤ 3.6 V

PMMCOREVx = 3,

20.0

2.4 V

≤ VCC ≤ 3.6 V

fSYSTEM_USB

Minimum processor frequency for USB operation

1.5

MHz

USB_wait

Wait state cycles during USB operation

cycles

(1)

It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be

tolerated during power up and operation.

(2)

USB operation with USB PLL enabled requires PMMCOREVx

≥ 2 for proper operation.

(3)

The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the

specified maximum frequency.

(4)

Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.

Submit Documentation Feedback

MSP430F5632IPZ Datasheet(PDF) 39 Page - Texas Instruments

MSP430F5632IPZ Datasheet(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL