MSP430F5632IPZ datasheet(57/101 Pages) TI

57 / 101 page

SDA

SCL

HD,DAT

SU,DAT

HD,STA

HIGH

LOW

BUF

HD,STA

SU,STA

SU,STO

MSP430F563x

www.ti.com

SLAS650A – JUNE 2010 – REVISED JULY 2010

USCI (I2C Mode) (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 7)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

tHD,DAT

Data hold time

2.2 V/3 V

tSU,DAT

Data setup time

2.2 V/3 V

250

fSCL ≤ 100 kHz

4.0

tSU,STO

Setup time for STOP

2.2 V/3 V

µs

fSCL > 100 kHz

0.6

2.2 V

600

tSP

Pulse width of spikes suppressed by input filter

3 V

600

Figure 7. I2C Mode Timing

12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

AVCC and DVCC are connected together,

AVCC

Analog supply voltage

AVSS and DVSS are connected together,

2.2

3.6

V(AVSS) = V(DVSS) = 0 V

V(Ax)

Analog input voltage range(2)

All ADC12 analog input pins Ax

AVCC

fADC12CLK = 5.0 MHz, ADC12ON = 1,

2.2 v

125

155

Operating supply current into

IADC12_A

REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV

µA

AVCC terminal

(3)

3 V

150

220

= 0

Only one terminal Ax can be selected at one

Input capacitance

2.2 V

time

Input MUX ON resistance

0 V

≤ VAx ≤ AVCC

200

1900

Ω

(1)

The leakage current is specified by the digital I/O input leakage.

(2)

The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the

reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are

required. See REF, External Reference and REF, Built-In Reference.

(3)

The internal reference supply current is not included in current consumption parameter IADC12.

12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

For specified performance of ADC12 linearity

fADC12CLK

2.2 V/3 V

0.45

4.8

5.4

MHz

parameters

Internal ADC12

fADC12OSC

ADC12DIV = 0, fADC12CLK = fADC12OSC

2.2 V/3 V

4.2

4.8

5.4

MHz

oscillator(1)

(1)

The ADC12OSC is sourced directly from MODOSC inside the UCS. At supply voltages below 2.2 V the ADC12OSC clock needs to be

divided by 2.

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