MSP430F5632IPZ datasheet(64/101 Pages) TI

64 / 101 page

= 3 k

Load

= 100 pF

Load

DAC Output

O/P(DAC12.x)

Load

Conversion 1

Conversion 2

OUT

Conversion 3

Glitch

Energy

±1/2 LSB

settleLH

settleHL

Conversion 1

Conversion 2

OUT

Conversion 3

10%

SRLH

SRHL

90%

10%

90%

MSP430F563x

SLAS650A – JUNE 2010 – REVISED JULY 2010

www.ti.com

Figure 11. Settling Time and Glitch Energy Testing

Figure 12. Slew Rate Testing

12-bit DAC, Dynamic Specifications (Continued)

(TA = 25°C unless otherwise noted)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

DAC12AMPx = {2, 3, 4},

DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h

3-dB bandwidth,

DAC12AMPx = {5, 6}, DAC12SREFx

BW–3dB

VDC = 1.5 V,

2.2 V/3 V

kHz

= 2,

180

VAC = 0.1 VPP (see Figure 13)

DAC12IR = 1, DAC12_xDAT = 800h

DAC12AMPx = 7, DAC12SREFx = 2,

550

DAC12IR = 1, DAC12_xDAT = 800h

DAC12_0DAT = 800h, No load,

DAC12_1DAT = 80h

↔ F7Fh, RLoad =

3 k

Ω,

–80

fDAC12_0OUT = 10 kHz at 50/50 duty

cycle

Channel-to-channel crosstalk(1)

2.2 V/3 V

(see Figure 14)

DAC12_0DAT = 80h

↔ F7Fh, RLoad =

3 k

Ω,

DAC12_1DAT = 800h, No load,

–80

fDAC12_0OUT = 10 kHz at 50/50 duty

cycle

(1)

RLoad = 3 kΩ, CLoad = 100 pF

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