MSP430F5632IPZ datasheet(17/101 Pages) TI

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MSP430F563x

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SLAS650A – JUNE 2010 – REVISED JULY 2010

Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the

device memory via the BSL is protected by user-defined password. For complete description of the features of

the BSL and its implementation, see the MSP430 Memory Programming User's Guide, TI literature number

SLAU265.

Table 7. BSL Functions

BSL FUNCTION

DEVICE OUTPUT SIGNAL

Data transmit

P1.1

Data receive

P1.2

Flash Memory

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

•

Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also

called information memory.

•

Segment A can be locked separately.

RAM Memory

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,

however all data is lost. Features of the RAM memory include:

•

RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.

•

Each sector 0 to n can be complete disabled, however data retention is lost.

•

Each sector 0 to n automatically enters low power retention mode when possible.

•

For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

Backup RAM Memory

The Backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during

operation from a backup supply in case the Battery Backup System module is implemented.

There are 8 bytes of Backup RAM available on MSP430F563x. It can be accessed wordwise via the control

registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

Peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using all

instructions. For complete module descriptions, see the MSP430x5xx/MSP430x6xx Family User's Guide,

literature number SLAU 208.

Digital I/O

There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete and port PJ contains four

individual I/O ports.

•

All individual I/O bits are independently programmable.

•

Any combination of input, output, and interrupt conditions is possible.

•

Programmable pullup or pulldown on all ports.

•

Programmable drive strength on all ports.

•

Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.

•

Read/write access to port-control registers is supported by all instructions.

•

Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).

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