MSP430F5632IPZ datasheet(53/101 Pages) TI

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SU,MI

HD,MI

UCLK

SOMI

SIMO

VALID,MO

HD,MO

CKPL =0

CKPL =1

LO/HI

1/f

UCxCLK

MSP430F563x

www.ti.com

SLAS650A – JUNE 2010 – REVISED JULY 2010

USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note

(1), Figure 3, and Figure 4)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

SMCLK, ACLK

fUSCI

USCI input clock frequency

fSYSTEM

MHz

Duty cycle = 50% ± 10%

1.8 V

PMMCOREV = 0

3 V

tSU,MI

SOMI input data setup time

2.4 V

PMMCOREV = 3

3 V

1.8 V

PMMCOREV = 0

3 V

tHD,MI

SOMI input data hold time

2.4 V

PMMCOREV = 3

3 V

UCLK edge to SIMO valid,

1.8 V

CL = 20 pF

3 V

PMMCOREV = 0

tVALID,MO

SIMO output data valid time(2)

UCLK edge to SIMO valid,

2.4 V

CL = 20 pF

3 V

PMMCOREV = 3

1.8 V

-10

CL = 20 pF

PMMCOREV = 0

3 V

-8

tHD,MO

SIMO output data hold time(3)

2.4 V

-10

CL = 20 pF

PMMCOREV = 3

3 V

-8

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).

For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.

(2)

Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing

diagrams in Figure 3 and Figure 4.

(3)

Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in

Figure 3 and Figure 4.

Figure 3. SPI Master Mode, CKPH = 0

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