MSP430F5632IPZ datasheet(52/101 Pages) TI

52 / 101 page

MSP430F563x

SLAS650A – JUNE 2010 – REVISED JULY 2010

www.ti.com

Battery Backup

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

TA = -40°C

0.43

VBAT = 1.7 V

TA = 25°C

0.52

DVCC not

µA

connected

TA = 60°C

0.58

RTC running

TA = 85°C

0.64

TA = -40°C

0.50

VBAT = 2.2 V

TA = 25°C

0.59

Current into VBAT terminal in case

DVCC not

IVBAT

µA

no primary battery is connected.

connected

TA = 60°C

0.64

RTC running

TA = 85°C

0.71

TA = -40°C

0.68

VBAT = 3 V

TA = 25°C

0.75

DVCC not

µA

connected

TA = 60°C

0.79

RTC running

TA = 85°C

0.86

General

VSVSH_I

T-

SVSHRL = 0

1.59

1.69

VSWITCH

Switch over level (VCC to VBAT)

CVCC = 4.7 µF

SVSHRL = 1

1.79

1.91

SVSHRL = 2

1.98

2.11

SVSHRL = 3

2.10

2.23

On-resistance of switch between

0 V

350

RON_VBAT

VBAT = 1.8 V

Ω

VBAT and VBAK

1.8 V

0.6

±5%

VBAT to ADC:

VBAT3

3 V

1.0

±5%

VBAT divide. VBAT3 ≠ VBAT /3

3.6 V

1.2

±5%

tSample,VBA

VBAT to ADC: Sampling time

ADC12ON = 1, Error of conversion

1000

required if VBAT3 selected.

result

≤ 1 LSB

VCHVx

Charger end voltage

CHVx = 2

2.65

2.7

2.9

CHCx = 1

RCHARGE

Charge limiting resistor

CHCx = 2

Ω

CHCx = 3

USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Internal: SMCLK, ACLK

fUSCI

USCI input clock frequency

External: UCLK

fSYSTEM

MHz

Duty cycle = 50% ± 10%

BITCLK clock frequency

fBITCLK

MHz

(equals baud rate in MBaud)

2.2 V

600

UART receive deglitch time(1)

3 V

600

(1)

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized their width should exceed the maximum specification of the deglitch time.

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