MSP430F5632IPZ datasheet(19/101 Pages) TI

19 / 101 page

MSP430F563x

www.ti.com

SLAS650A – JUNE 2010 – REVISED JULY 2010

Table 9. Default Mapping (continued)

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

PM_UCA0TXD/PM_UCA0 USCI_A0 UART TXD (direction controlled by USCI - output) / USCI_A0 SPI slave

P2.4/P2MAP4

SIMO

in master out (direction controlled by USCI)

PM_UCA0RXD/PM_UCA0

USCI_A0 UART RXD (direction controlled by USCI - input) / USCI_A0 SPI slave

P2.5/P2MAP5

SOMI

out master in (direction controlled by USCI)

P2.6/P2MAP6

PM_NONE

DVSS

P2.7/P2MAP7

PM_NONE

DVSS

Oscillator and System Clock

The clock system in the MSP430F563x family of devices is supported by the Unified Clock System (UCS)

module that includes support for a 32 kHz watch crystal oscillator (XT1 LF mode - XT1 HF mode not supported),

an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO),

an integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS

module is designed to meet the requirements of both low system cost and low-power consumption. The UCS

module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,

stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO

provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the following

clock signals:

•

Auxiliary clock (ACLK), sourced from a 32 kHz watch crystal (XT1), a high-frequency crystal (XT2), the

internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal

digitally-controlled oscillator DCO.

•

Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made

available to ACLK.

•

Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources made available to ACLK.

•

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

Power Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor

(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power-on and power-off. The

SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply

voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not

automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with

32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication

as well as signed and unsigned multiply and accumulate operations.

Real-Time Clock (RTC_B)

The RTC_B module can be configured for real-time clock (RTC) and calendar mode providing seconds, minutes,

hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which

compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports

flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in

LPM3.5 mode and operation from a backup supply.

Watchdog Timer (WDT_A)

The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

Submit Documentation Feedback

MSP430F5632IPZ Datasheet(PDF) 19 Page - Texas Instruments

MSP430F5632IPZ Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL