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C6416 Datasheet(PDF) 32 Page - Texas Instruments |
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C6416 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 134 page ![]() SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXEDPOINT DIGITAL SIGNAL PROCESSORS SGUS050A − JANUARY 2004 − REVISED MARCH 2004 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 signal groups description (continued) HHWIL/PTRDY HCNTL0/PSTOP HCNTL1/PDEVSEL Data Register Select Half-Word Select Control HPI† (Host-Port Interface) 32 HD[31:0]/AD[31:0] HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME (HPI16 ONLY) † For the C6415 and C6416 devices, these HPI pins are MUXed with the PCI peripheral. By default, these signals function as HPI. For more details on these MUXed pins, see the Device Configurations section of this data sheet. For the C6414 device, these HPI pins are not MUXed; the C6414 device does not support the PCI peripheral. ‡ For the C6415 and C6416 devices, these PCI pins (excluding PCBE0 and XSP_CS) are MUXed with the HPI, McBSP2, or GPIO peripherals. By default, these signals function as HPI, McBSP2, and no function, respectively. For more details on these MUXed pins, see the Device Configurations section of this data sheet. For the C6414 device, the HPI, McBSP2, and GPIO peripheral pins are not MUXed; the C6414 device does not support the PCI peripheral. § For the C6414 device, these pins are “Reserved (leave unconnected, do not connect to power or ground).” HD[31:0]/AD[31:0] HR/W/PCBE2 HDS2/PCBE1 PCBE0§ GP12/PGNT GP11/PREQ GP14/PCLK HINT/PFRAME GP13/PINTA Data/Address Arbitration 32 Clock Control PCI Interface‡ (C6415 and C6416 Only) HAS/PPAR GP15/PRST HRDY/PIRDY HCNTL0/PSTOP HHWIL/PTRDY GP10/PCBE3 GP9/PIDSEL HCNTL1/PDEVSEL HDS1/PSERR Error Command Byte Enable Serial EEPROM DX2/XSP_DO XSP_CS§ CLKX2/XSP_CLK DR2/XSP_DI HCS/PPERR Figure 3. Peripheral Signals (Continued) |
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