C6416 datasheet(67/134 Pages) TI1

67 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

clock PLL

Most of the internal C64x

 DSP clocks are generated from a single source through the CLKIN pin. This source

clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock, or

bypasses the PLL to become the internal CPU clock.

To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5

shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.

To minimize the clock jitter, a single clean power supply should power both the C64x

 DSP device and the

external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input

clock timing requirements, see the input and output clocks electrical section.

Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source

must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended

ranges of supply voltage and operating case temperature table and the input and output clocks electrical

section). Table 31 lists some examples of compatible CLKIN external clock sources:

Table 31. Compatible CLKIN External Clock Sources

COMPATIBLE PARTS FOR

EXTERNAL CLOCK SOURCES (CLKIN)

PART NUMBER

MANUFACTURER

JITO-2

Fox Electronix

Oscillators

STA series, ST4100 series

SaRonix Corporation

Oscillators

SG-636

Epson America

342

Corning Frequency Control

PLL

ICS525-02

Integrated Circuit Systems

C6416 Datasheet(PDF) 67 Page - Texas Instruments