C6416 datasheet(42/134 Pages) TI1

42 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

SIGNAL

TYPE†

IPD/

‡

DESCRIPTION

NAME

NO.

TYPE†

IPD/

IPU‡

DESCRIPTION

RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS

RESET

AB5

Device reset

NMI

IPD

Nonmaskable interrupt, edge-driven (rising edge)

GP7/EXT_INT7

General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The

default after reset setting is GPIO enabled as input-only.

GP6/EXT_INT6

I/O/Z

IPU

General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The

default after reset setting is GPIO enabled as input-only.

When these pins function as External Interrupts [by selecting the corresponding interrupt

GP5/EXT_INT5

AA5

I/O/Z

IPU

• When these pins function as External Interrupts [by selecting the corresponding interrupt

enable register bit (IER.[7:4])], they are edge-driven and the polarity can be

GP4/EXT_INT4

enable register bit (IER.[7:4])], they are edge-driven and the polarity can be

independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]).

GP15/PRST§

General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.

GP14/PCLK§

GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.

GP13/PINTA§

GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.

GP12/PGNT§

GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.

GP11/PREQ§

GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.

GP10/PCBE3§

I/O/Z

GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.

GP9/PIDSEL§

I/O/Z

GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.

GP3

AA6

IPD

GPIO 3 pin (I/O/Z). The default after reset setting is GPIO 3 enabled as input-only.

GP0

IPD

GPIO 0 pin.

The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only)

[default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT)

signal (output only).

CLKS2/GP8§¶

I/O/Z

IPD

McBSP2 external clock source (CLKS2) [input only] [default] or this pin can be pro-

grammed as a GPIO 8 pin (I/O/Z).

CLKOUT6/GP2§¶

T10

I/O/Z

IPD

Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a

GPIO 2 pin (I/O/Z).

CLKOUT4/GP1§¶

I/O/Z

IPD

Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a

GPIO 1 pin (I/O/Z).

HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only]

PCI_EN

IPD

PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or

PCI peripherals (for the C6415 and C6416 devices). This pin works in conjunction with the

MCBSP2_EN pin to enable/disable other peripherals (for more details, see the Device Con-

figurations section of this data sheet).

The C6414 device does not support the PCI peripheral; for proper device operation, do not

oppose the internal pulldown (IPD) on this pin.

HINT/PFRAME§

I/O/Z

Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z)

HCNTL1/

PDEVSEL§

I/O/Z

Host control − selects between control, address, or data registers (I) [default] or PCI device

select (I/O/Z).

HCNTL0/

PSTOP§

I/O/Z

Host control − selects between control, address, or data registers (I) [default] or PCI stop

(I/O/Z)

HHWIL/PTRDY§

I/O/Z

Host half-word select − first or second half-word (not necessarily high or low order)

[For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z)

HR/W/PCBE2§

I/O/Z

Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)

† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-k

Ω resistor should be used.)

§ For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.

The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions

for this device.

¶ For the C6414 device, only these pins are multiplexed pins.

C6416 Datasheet(PDF) 42 Page - Texas Instruments

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