C6416 datasheet(33/134 Pages) TI1

33 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

signal groups description (continued)

McBSPs

(Multichannel Buffered

Serial Ports)

CLKX0

FSX0

DX0

CLKR0

FSR0

DR0

CLKS0

Transmit

McBSP0

Receive

Clock

CLKX1/URADDR4†

FSX1/UXADDR3†

DX1/UXADDR4†

CLKR1/URADDR2†

FSR1/UXADDR2†

DR1/UXADDR1†

CLKS1/URADDR3†

Transmit

McBSP1

Receive

Clock

CLKX2/XSP_CLK†

FSX2

DX2/XSP_DO†

CLKR2

FSR2

DR2/XSP_DI†

CLKS2/GP8‡

Transmit

McBSP2

Receive

Clock

† For the C6415 and C6416 devices, these McBSP2 and McBSP1 pins are MUXed with the PCI and UTOPIA peripherals, respectively.

By default, these signals function as McBSP2 and McBSP1, respectively. For more details on these MUXed pins, see the Device

Configurations section of this data sheet.

For the C6414 device, these McBSP2 and McBSP1 peripheral pins are not MUXed; the C6414 device does not support PCI and

UTOPIA peripherals.

‡ The McBSP2 clock source pin (CLKS2, default) is MUXed with the GP8 pin. To use this MUXed pin as the GP8 signal, the appropriate

GPIO register bits (GP8EN and GP8DIR) must be properly enabled and configured. For more details, see the Device Configurations

section of this data sheet.

Figure 3. Peripheral Signals (Continued)

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