C6416 datasheet(41/134 Pages) TI1

41 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions

SIGNAL

TYPE†

IPD/

IPU‡

DESCRIPTION

NAME

NO.

TYPE†

IPD/

IPU‡

DESCRIPTION

CLOCK/PLL CONFIGURATION

CLKIN

IPD

Clock Input. This clock is the input to the on-chip PLL.

CLKOUT4/GP1§

I/O/Z

IPD

Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a

GPIO 1 pin (I/O/Z).

CLKOUT6/GP2§

T10

I/O/Z

IPD

Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a

GPIO 2 pin (I/O/Z).

CLKMODE1

IPD

Clock mode select

• Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12.

CLKMODE0

IPD

• Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12.

For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL

section of this data sheet.

PLLV¶

PLL voltage supply

JTAG EMULATION

TMS

V14

IPU

JTAG test-port mode select

TDO

W16

O/Z

IPU

JTAG test-port data out

TDI

AA17

IPU

JTAG test-port data in

TCK

Y15

IPU

JTAG test-port clock

TRST

Y14

IPD

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG

Compatibility Statement section of this data sheet.

EMU11

V15

I/O/Z

IPU

Emulation pin 11. Reserved for future use, leave unconnected.

EMU10

Y16

I/O/Z

IPU

Emulation pin 10. Reserved for future use, leave unconnected.

EMU9

T14

I/O/Z

IPU

Emulation pin 9. Reserved for future use, leave unconnected.

EMU8

U14

I/O/Z

IPU

Emulation pin 8. Reserved for future use, leave unconnected.

EMU7

AB18

I/O/Z

IPU

Emulation pin 7. Reserved for future use, leave unconnected.

EMU6

AA16

I/O/Z

IPU

Emulation pin 6. Reserved for future use, leave unconnected.

EMU5

W15

I/O/Z

IPU

Emulation pin 5. Reserved for future use, leave unconnected.

EMU4

AB17

I/O/Z

IPU

Emulation pin 4. Reserved for future use, leave unconnected.

EMU3

W14

I/O/Z

IPU

Emulation pin 3. Reserved for future use, leave unconnected.

EMU2

AA15

I/O/Z

IPU

Emulation pin 2. Reserved for future use, leave unconnected.

EMU1

EMU0

T13

V13

I/O/Z

IPU

Emulation [1:0] pins

• Select the device functional mode of operation

EMU[1:0]

Operation

Boundary Scan/Normal Mode (see Note)

Reserved

Emulation/Normal Mode [default] (see the IEEE 1149.1 JTAG

Compatibility Statement section of this data sheet)

Normal mode refers to the DSPs normal operational mode, when the DSP is free running. The

DSP can be placed in normal operational mode when the EMU[1:0] pins are configured for

either Boundary Scan or Emulation.

Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown

(IPD) on the TRST signal must not be opposed in order to operate in Normal mode.

For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-k

Ω resister.

† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-k

Ω resistor should be used.)

§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.

¶ PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.

# A = Analog signal (PLL Filter)

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