C6416 datasheet(74/134 Pages) TI1

74 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

IEEE 1149.1 JTAG compatibility statement

The SMJ320C6414/15/16 DSP requires that both TRST and RESET be asserted upon power up to be properly

initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are

required for proper operation.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the

DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface

and DSP’s emulation logic in the reset state.

TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise

the DSP’s boundary scan functionality.

For maximum reliability, the SMJ320C6414/15/16 DSP includes an internal pulldown (IPD) on the TRST pin to

ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be

properly initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers

may not drive TRST high but expect the use of a pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the DSP after power up and externally drive

TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the

low-to-high transition of TRST must be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins

configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see

the terminal functions section of this data sheet.

EMIF device speed

The rated EMIF speed, referring to both EMIFA and EMIFB, of these devices only applies to the SDRAM

interface when in a system that meets the following requirements:

−

1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF

−

up to 1 CE space of buffers connected to EMIF

−

EMIF trace lengths between 1 and 3 inches

−

166-MHz SDRAM for 133-MHz operation (applies only to EMIFA)

−

143-MHz SDRAM for 100-MHz operation

Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.

Verification of AC timings is mandatory when using configurations other than those specified above. TI

recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.

To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models

for Timing Analysis application report (literature number SPRA839).

To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see

the Terminal Functions table for the EMIF output signals).

C6416 Datasheet(PDF) 74 Page - Texas Instruments

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