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C6416 Datasheet(PDF) 44 Page - Texas Instruments |
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C6416 Datasheet(HTML) 44 Page - Texas Instruments |
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44 / 134 page  SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXEDPOINT DIGITAL SIGNAL PROCESSORS SGUS050A − JANUARY 2004 − REVISED MARCH 2004 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE† IPD/ ‡ DESCRIPTION NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only] (CONTINUED) PCBE0 Y3 I/O/Z PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off. For the C6414 device this pin is “Reserved (leave unconnected, do not connect to power or ground).” XSP_CS AA3 O IPD PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is tied-off. For the C6414 device this pin is “Reserved (leave unconnected, do not connect to power or ground).” CLKX2/ XSP_CLK§ W5 I/O/Z IPD McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O). DR2/XSP_DI§ Y4 I IPU McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is connected to the output data pin of the serial PROM. DX2/XSP_DO§ R9 O/Z IPU McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode, this pin is connected to the input data pin of the serial PROM. GP15/PRST§ J8 General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default. GP14/PCLK§ G5 GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default. GP13/PINTA§ G4 GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. GP12/PGNT§ J7 I/O/Z GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default. GP11/PREQ§ H6 I/O/Z GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. GP10/PCBE3§ L7 GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. GP9/PIDSEL§ K6 GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. EMIFA (64-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY||k ACE3 K20 O/Z IPU EMIFA memory space enables ACE2 L17 O/Z IPU EMIFA memory space enables • Enabled by bits 28 through 31 of the word address ACE1 J21 O/Z IPU • Enabled by bits 28 through 31 of the word address • Only one pin is asserted during any external data access ACE0 K19 O/Z IPU • Only one pin is asserted during any external data access ABE7 P19 O/Z IPU ABE6 U22 O/Z IPU ABE5 T22 O/Z IPU EMIFA byte-enable control Decoded from the low-order address bits. The number of address bits or byte enables ABE4 R21 O/Z IPU EMIFA byte-enable control • Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. ABE3 M17 O/Z IPU used depends on the width of external memory. • Byte-write enables for most types of memory ABE2 M18 O/Z IPU • Byte-write enables for most types of memory • Can be directly connected to SDRAM read and write mask signal (SDQM) ABE1 H22 O/Z IPU Can be directly connected to SDRAM read and write mask signal (SDQM) ABE0 L19 O/Z IPU APDT L20 O/Z IPU EMIFA peripheral data transfer, allows direct transfer between external peripherals † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.) § For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions for this device. || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. |
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