C6416 datasheet(94/134 Pages) TI1

94 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

SYNCHRONOUS DRAM TIMING (CONTINUED)

timing requirements for synchronous DRAM cycles for EMIFB module† (see Figure 27)

NO.

MIN

MAX

UNIT

tsu(EDV-EKO1H)

Setup time, read EDx valid before ECLKOUTx high

2.1

th(EKO1H-EDV)

Hold time, read EDx valid after ECLKOUTx high

2.5

† These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a

“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM

memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and

BSDCAS, BSDWE, and BSDRAS (for EMIFB)].

switching characteristics over recommended operating conditions for synchronous DRAM cycles

for EMIFB module† (see Figure 27−Figure 34)

NO.

PARAMETER

MIN

MAX

UNIT

td(EKO1H-CEV)

Delay time, ECLKOUTx high to CEx valid

1.3

6.4

td(EKO1H-BEV)

Delay time, ECLKOUTx high to BEx valid

6.4

td(EKO1H-BEIV)

Delay time, ECLKOUTx high to BEx invalid

1.3

td(EKO1H-EAV)

Delay time, ECLKOUTx high to EAx valid

6.4

td(EKO1H-EAIV)

Delay time, ECLKOUTx high to EAx invalid

1.3

td(EKO1H-CASV)

Delay time, ECLKOUTx high to SDCAS valid

1.3

6.4

td(EKO1H-EDV)

Delay time, ECLKOUTx high to EDx valid

6.4

td(EKO1H-EDIV)

Delay time, ECLKOUTx high to EDx invalid

1.3

td(EKO1H-WEV)

Delay time, ECLKOUTx high to SDWE valid

1.3

6.4

td(EKO1H-RAS)

Delay time, ECLKOUTx high to SDRAS valid

1.3

6.4

td(EKO1H-ACKEV)

Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only)

1.3*

6.4*

td(EKO1H-PDTV)

Delay time, ECLKOUTx high to PDT valid

1.3

6.4

*This parameter is not production tested.

† These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a

“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM

memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and

BSDCAS, BSDWE, and BSDRAS (for EMIFB)].

C6416 Datasheet(PDF) 94 Page - Texas Instruments

C6416 Datasheet(HTML) 94 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL