C6416 datasheet(17/134 Pages) TI1

17 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

peripheral register descriptions (continued)

Table 7. EDMA Registers

HEX ADDRESS RANGE

ACRONYM

01A0 FF9C

EPRH

Event polarity high register

01A0 FFA4

CIPRH

Channel interrupt pending high register

01A0 FFA8

CIERH

Channel interrupt enable high register

01A0 FFAC

CCERH

Channel chain enable high register

01A0 FFB0

ERH

Event high register

01A0 FFB4

EERH

Event enable high register

01A0 FFB8

ECRH

Event clear high register

01A0 FFBC

ESRH

Event set high register

01A0 FFC0

PQAR0

Priority queue allocation register 0

01A0 FFC4

PQAR1

Priority queue allocation register 1

01A0 FFC8

PQAR2

Priority queue allocation register 2

01A0 FFCC

PQAR3

Priority queue allocation register 3

01A0 FFDC

EPRL

Event polarity low register

01A0 FFE0

PQSR

Priority queue status register

01A0 FFE4

CIPRL

Channel interrupt pending low register

01A0 FFE8

CIERL

Channel interrupt enable low register

01A0 FFEC

CCERL

Channel chain enable low register

01A0 FFF0

ERL

Event low register

01A0 FFF4

EERL

Event enable low register

01A0 FFF8

ECRL

Event clear low register

01A0 FFFC

ESRL

Event set low register

01A1 0000 − 01A3 FFFF

–

Reserved

C6416 Datasheet(PDF) 17 Page - Texas Instruments

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