C6416 datasheet(82/134 Pages) TI1

82 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

INPUT AND OUTPUT CLOCKS (CONTINUED)

timing requirements for ECLKIN for EMIFA and EMIFB†‡§ (see Figure 19)

NO.

MIN

MAX

UNIT

tc(EKI)

Cycle time, ECLKIN

6¶*

16P*

tw(EKIH)

Pulse duration, ECLKIN high

2.7*

tw(EKIL)

Pulse duration, ECLKIN low

2.7*

tt(EKI)

Transition time, ECLKIN

*This parameter is not production tested.

† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

‡ The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

§ These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are

prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.

¶ Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.

On the 7E3 and 6E3 devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. On the 5E0 devices,

100-MHz operation is achievable if the requirements of the EMIF Device Speed section are met.

ECLKIN

Figure 19. ECLKIN Timing for EMIFA and EMIFB

switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and

EMIFB modules§#||k (see Figure 20)

NO.

PARAMETER

MIN

MAX

UNIT

tJ(EKO1)

Period jitter, ECLKOUT1

±175h*

tw(EKO1H)

Pulse duration, ECLKOUT1 high

EH − 0.7*

EH + 0.7*

tw(EKO1L)

Pulse duration, ECLKOUT1 low

EL − 0.7*

EL + 0.7*

tt(EKO1)

Transition time, ECLKOUT1

td(EKIH-EKO1H)

Delay time, ECLKIN high to ECLKOUT1 high

td(EKIL-EKO1L)

Delay time, ECLKIN low to ECLKOUT1 low

*This parameter is not production tested.

§ These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are

prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.

# The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

|| E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.

kEH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA or EMIFB.

hThis period jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.

C6416 Datasheet(PDF) 82 Page - Texas Instruments

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