C6416 datasheet(72/134 Pages) TI1

72 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Reserved

Enable or

Non-Enabled

Interrupt Wake

Enabled

Interrupt Wake

PD3

PD2

PD1

R/W-0

Legend: R/W−x = Read/write reset value

NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other

bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).

Figure 9. PWRD Field of the CSR Register

Power-down mode PD1 takes effect eight to nine clock cycles after the instruction that sets the PWRD bits in the

CSR. If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where

PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed

first, then the program execution returns to the instruction where PD1 took effect.

PD2 and PD3 modes can only be aborted by device reset. Table 33 summarizes all the power-down modes.

Table 33. Characteristics of the Power-Down Modes

PRWD FIELD

(BITS 15−10)

POWER-DOWN

MODE

WAKE-UP METHOD

EFFECT ON CHIP’S OPERATION

000000

No power-down

—

001001

PD1

Wake by an enabled interrupt

CPU halted (except for the interrupt logic)

Power-down mode blocks the internal clock inputs at the

010001

PD1

Wake by an enabled or

non-enabled interrupt

Power-down mode blocks the internal clock inputs at the

boundary of the CPU, preventing most of the CPU’s logic from

switching. During PD1, EDMA transactions can proceed

between peripherals and internal memory.

011010

PD2†

Wake by a device reset

Output clock from PLL is halted, stopping the internal clock

structure from switching and resulting in the entire chip being

halted. All register and internal RAM contents are preserved. All

functional I/O “freeze” in the last state when the PLL clock is

turned off.

011100

PD3†

Wake by a device reset

Input clock to the PLL stops generating clocks. All register and

internal RAM contents are preserved. All functional I/O “freeze” in

the last state when the PLL clock is turned off. Following reset, the

PLL needs time to re-lock, just as it does following power-up.

Wake-up from PD3 takes longer than wake-up from PD2 because

the PLL needs to be re-locked, just as it does following power-up.

All others

Reserved

—

† When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or

peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,

peripherals will not operate according to specifications.

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